The present invention generally relates to methods of designing a three-dimensional semiconductor chip including a plurality of layers, an apparatus for effecting the methods, and a storage medium including an executable program for effecting the methods.
A plurality of device-containing layers may be vertically integrated to form a three-dimensionally integrated semiconductor chip. Typically, each device-containing layer includes a semiconductor layer and a metal interconnect layer. Each semiconductor layer includes an integrated circuit of semiconductor devices, and each of the metal interconnect layer includes metal interconnect structures embedded in at least one dielectric layer. The plurality of device-containing layers are individually and separately formed employing conventional semiconductor processing steps, and then vertically stacked to form the three-dimensionally integrated semiconductor chip.
FIG. 1 schematically shows a prior art three-dimensionally integrated semiconductor chip, which includes a first-device-containing layer labeled “Base, I/O, and Test Circuits,” a second device-containing layer labeled “First Processors,” a third device-containing layer labeled “Second Processors,” and a fourth device-containing layer labeled “Accelerators.” Each device-containing layer includes a plurality of “functional blocks,” which are functional units of an integrated circuit within a device-containing layer. A functional block may be a single chiplet or a set of multiple chiplets. Alternatively, a plurality of functional blocks may form a single chiplet. The functional blocks of the prior art three-dimensionally integrated semiconductor chip are schematically shown as rectangles. The different functions that the functional blocks may perform are schematically shown by the differences in the hatching style of the functional blocks.
Each device-containing layer further includes a plurality of interlayer interconnect structure arrays 10 that include vertical interconnect structures. The vertical interconnect structures provide electrical connection between vertically neighboring device-containing layers. The electrical connections provided by the vertical interconnect structures are schematically shown by arrows between the interlayer interconnect structure arrays.
FIG. 2 shows an exemplary layout of functional blocks and interlayer interconnect structure arrays within a device-containing layer. The exemplar prior art layout includes a first functional block 1, a second functional block 2, a third functional block 3, a fourth functional block 4, a fifth functional block 5, a sixth functional block 6, a seventh functional block 7, an eighth functional block 8, a ninth functional block 9, a first interlayer interconnect structure array 12, a second interlayer interconnect structure array 13, a third interlayer interconnect structure array 14, and a fourth interlayer interconnect structure array 15. The first interlayer interconnect structure array 12 is located between the first functional block 1 and the second functional block 2, the second interlayer interconnect structure array 13 is located between the first functional block 1 and the third functional block 3, the third interlayer interconnect structure array 14 is located between the first functional block 1 and the fourth functional block 4, and the fourth interlayer interconnect structure array 15 is located between the first functional block 1 and the fifth functional block 5. Additional interlayer interconnect structure arrays that are not placed directly adjacent to the first functional block 1 are not shown for clarity. The placement of the interlayer interconnect structure arrays (12, 13, 14, 15) at the boundary between the first functional block 1 and other neighboring functional blocks (2, 3, 4, 5) minimized wiring length within the device-containing layer.
Three-dimensional integration provides various advantages for a semiconductor chip. Such advantages include reduced wirelength, increased packaging density, modularity, and heterogeneous integration of disparate technologies.